Some processors, in particular, general purpose processors, allow a type of caching (called “memory type”) to be specified for selected areas of main memory. For example, page cacheability attributes and Memory Type Range Registers (MTRRs) can be used to determine cache attributes of memory bus accesses. Such memory types can include Uncacheable (UC), Write-Through (WT), Write Back (WB), Write Protected (WP) and Write Combining (WC) memory types. If the UC memory type is specified, the selected area is not cached. For the WT memory type, writes to and reads from the selected area are cached. Reads come from cache lines on cache hits and read misses cause cache line fills. All writes are written to a cache line and through to the main memory. The WT mechanism enforces coherency between the cache and the main memory. With the WB memory type, writes to and reads from main memory are also cached. Reads come from cache lines on cache hits, and read misses cause cache line fills. Write misses cause cache line fills, and writes are performed entirely in the cache, when possible. A WB operation is triggered when cache lines need to be deallocated. For a WP memory type, reads come from cache lines when possible, and read misses cause cache line fills. Writes are propagated to the system bus and cause corresponding cache lines on all processors on the bus to be invalidated. When WC is used, main memory locations are not cached, and writes may be delayed and combined in a write buffer to reduce memory accesses.
Memory regions that are marked as UC can only be read and written in sub-cache line sizes, resulting in low performance for those memory regions. The WC memory type offers higher performance cache line writes, but reads are still low performance. The WT and WB memory types offer high performance cache line reads and writes but are cacheable types.